Clock timing jitter can be a limiting factor in high performance Analog-to-Digital Converters (ADCs). ADCs typically include a module or circuit that periodically samples an analog input signal according to a timing or clock signal. Jitter, as discussed herein, generally relates to errors resulting from a departure from a precisely periodic sample time/interval. Such errors result from jitter that occurs in both the module that samples signals (aperture jitter) and in the clock signal itself (clock jitter).
Jitter is a random process that results in variations in the spacing of sampled pulses within an ADC. The digital reconstruction of signals captured by ADCs assumes uniform sampling in time, such that when there is non-uniform sampling, noise-like errors are introduced into the digital signal stream. ADCs commercially available for use in high-speed applications, such as Radio Frequency (RF) receivers, are limited in dynamic range to such an extent by timing jitter, that it constrains the overall receiver capability.
One measure of quality of ADCs is referred to as an Effective Number of Bits (ENOB). The resolution of an ADC is commonly specified by the number of bits used to represent the analog value, in principle giving 2N signal levels for any N-bit signal. The value of ENOB specifies the number of bits in the digitized signal above the noise floor. FIG. 1A and FIG. 1B show relationship of ENOB obtainable for ADCs as a function of their maximum sample rate (fs) and the timing jitter (σj). Unless otherwise noted, clock or timing jitter levels described herein are root-mean-square (RMS) values. FIG. 2 shows similar constraints, expressing dynamic range in decibels (dB). In the 1990s and early 2000s it was not uncommon for total jitter to have RMS jitter value of above 1 picosecond (ps). A jitter value of 1 ps limits a 10-bit ADC to a maximum conversion rate of around 100 MHz. Each reduction in jitter by a factor of two enables either a factor of two, higher conversion rate or an additional ENOB.
The total timing jitter is the root-sum-square combination of clock jitter and aperture jitter. An article by R. H. Walden, entitled “Analog-to-Digital Conversion in the Early 21st Century,” published in the IEEE MTT Workshop on Ultrafast Analog-to-Digital (A/D) Conversion Techniques and its Applications, 5 (2007), reports that aperture jitter has been reduced below a value of 100 ps for high end components as of 2006. Table 1 shows values for aperture jitter found in the literature for high end commercial ADCs from companies including Texas Instruments and Analog Devices. The table shows that 60-80 femtoseconds (fs) is a state-of the art value. Walden predicts aperture jitter will reach 25 fs for electronic sampling circuits.
TABLE IRepresentative Aperture JitterAperture Jitter (fs)Reference70Linear Technology, Understanding the Effect(140 MSPS of Clock Jitter on High Speed ADCs-Designsystem)Note 1013, Derek Redmayne (LTC ApplicationsEngineer), et al.60Analog Devices, MT-007 TUTORIAL, Aperture (125 MSPS, Time, Aperture Jitter, Aperture Delay Time-14 bit)Removing the Confusion by Walt Kester.25R. H. Walden, Analog-to-Digital Conversion in (predicted in the Early 21st Century, inIEEE MTT Workshop onnear future) Ultrafast Analog-to-Digital A/D) Conversion(Techniques and its Applications, 5 (2007).80Texas Instruments, Optimizing ADC (135 MSPS, SNR by Reducing Sampling Jitter 16 bit)with Proper Clocking Design , By Lin Wu, September 2009 http://www.wirelessdesignasia.com/.60Analog Devices, MT-007 TUTORIAL, Aperture(100 MSPS, Time, Aperture Jitter, Aperture Delay Time- 16 bit)Removing the Confusion by Walt Kester.<10Alan M. Braun et al, Compact, high-power, low-jitter, (Optical)semiconductor modelocked laser module for photonic A/D converter applications, Enabling Photonic Tech-nologies for Aerospace Applications V, Andrew R.Pirich, et al, Eds, Proc of SPIE Vol. 5104 (2003).
Clock jitter is highly dependent on the type of oscillator (a reference source to a timing or clock circuit), the frequency of the oscillator, whether it is a sinusoid or a square wave, etc., and whether it is for a fixed-frequency or a variable-rate clock. Fixed frequency oscillators providing sinusoidal signals, such as crystal oscillators, have demonstrated the lowest timing jitter available in the literature. Unfortunately these sources are limited to frequencies below about 200 MHz. Higher frequency clocks and variable speed clocks are typically based on Phase-Lock Loop (PLL) circuits, such as the one shown in FIG. 3. Square wave clocks appear to have more jitter than sinusoidal clocks but the sampling circuits have lower aperture jitter.
The PLL circuit shown in FIG. 3 is representative of a typical timing circuit 100. The input periodic reference (FREF) is generally of a lower frequency with relatively less jitter than the periodic output signal (FCLK). As the frequency of the output high-speed clock signal FCLK increases, so does the clock jitter. The PLL circuit 100 maintains a phase relationship between the high-frequency clock output signal and the input reference signal. Since the frequencies of the two singles differ some form of scaling is generally provided before phases of the two signals are compared by a phase comparator 102. As shown, the reference signal is divided by a first value, M in an input scaler 104. The output signal is divided by a second value, N, in an output pre-scaler 106, such that the periods of the scaled input and output signals are substantially equivalent. Phases of the two scaled signals are compared at the phase detector 102, which provides an output signal indicative of a phase offset between the two signals. The output of the phase detector can be filtered by a loop filter 108, as shown. The filtered output phase difference signal can be used to drive a voltage controlled oscillator 110 providing a high frequency of the signal phase locked to the input reference signal. In this example, voltage controlled oscillator output is further divided by a factor of two in a post-scaler 112 to provide an output clock signal at the desired clock frequency.
Oscillators are characterized by their phase noise, which is generally very high at frequencies within tens of kilohertz of the center frequency and abates at more distant frequencies. It hits a thermal noise floor at more distant offset frequencies. The integrated phase noise can be converted to timing jitter, for example, as described in Analog Devices publication MT-008, entitled “Converting Oscillator Phase Noise to Time Jitter,” by Walt Kester, October 2008.
Table 2 shows clock jitter levels of 200-450 fs for high-performance clocks found in the literature from manufacturers of ADC components and boards. All of these clocks ran at rates at or below 1 GHz. The clock described in Ref 3 was exactly 1 GHz and has the largest jitter at 450 fs.
TABLE 2Representative Clock JitterClock Jitter (fs)Reference300Joeger Enterprises, MODEL ADC 125/16 “VME”DUAL CHANNEL, HIGH PERFORMANCE, 125Mhz, 16 BIT ADC DAUGHTER BOARD.401National Semiconductor, Clocking High-Speed A/DConverters, App Note 1558. James Cali. January 2007.192National Semiconductor, LMK04000 Family, Low-Noise Clock Jitter Cleaner with Cascaded PLLs, Jul. 24, 2009.450E2V, High-Speed ADC Input Clock Issues-Application Note.200MAXIM, Design Challenges for an Ultra-Low-Jitter Clock Synthesizer-APPLICATION NOTE 4336, By: Paul Jones, Tanja Hofner, Dec. 23, 2008.10-100, (i) J. B. Schlager, Senior Member, IEEE, et al, Passively optical Mode-Locked Waveguide Laser With Low Residual Jitter,  IEEE PHOT TECHNOLOGY LET, SEPTEMBER 2002.(ii) Alan M. Braun et al, Compact, high-power,  low-jitter, semiconductor modelocked laser module for  photonic A/D converter applications, Enabling Photonic  Technologies for Aerospace Applications V, Andrew R.  Pirich, et al , Eds, Proc of SPIE Vol. 5104 (2003).(iii) George C. Valley et al, Photonic analog-to-digital converters: fundamental and practical limits, Integrated  Optical Devices, Nanostructures, and Displays, SPIE Volume: 5618, Keith Lewis Ed., November 2004.
Descriptions of oscillators and PLL-based clocks with the lowest phase noises at frequencies of about 100 MHz to about 12 GHz that the inventor could find in the open literature at the time of filing are described in “Ultra Low Phase Noise 200 MHz to 12 GHz Multiplied Crystal Oscillators,” Microwave Journal, Oct. 1, 2009, by Wenzel Associates, with additional listings available online at www.wenzel.com contain. A 2 GHz clock with about 450 fs of jitter is available from Wenzel Associates, Inc. of Austin, Tex. It is derived from a 100 MHz input (e.g., from a crystal oscillator) with about 70 fs of jitter. In the conversion process from the 100 MHz reference to the 2 GHz output frequency, there are several stages of multiplication and filtering, for example, one stage providing a 200 MHz signal with about 100 fs of RMS jitter. Table 3 provides conversion of the reported phase noise levels, via known formulas (e.g., see Analog Devices, “MT-008: Converting Oscillator Phase Noise to Time Jitter,” by Walt Kester, October 2008), into clock jitter. Table 3 also shows a corresponding limit of ADC performance (e.g., jitter-limited ENOB) due to the associated jitter for a maximum sample rate at half the given clock rate.
TABLE 3Low Timing Jitter ClocksMax Sample JITTERSNRJitter-LimitedCLK (MHz)Rate (MHz)(Sec)JITTERENOB800040001.1E−12315.1512025608.9E−13376.1256012805.6E−13477.8200010004.5E−13518.510005002.8E−136110.15002502.0E−137011.62001001.0E−138414.0100507.1E−149315.5
As shown in Table 3, jitter values range from 70 fs for a 100 MHz crystal oscillator to more than 1 ps for an 8 GHz clock. Several multiplication stages upconvert the 100 MHz or other reference to the final high-speed clock. The ENOB levels drop quite substantially from 15.5 bits to 5 bits across this range of frequencies. As described above, the total jitter levels for an ADC include aperture jitter (nominally 70 fs) added in quadrature to clock jitter.
Thus, higher speed clocks are susceptible to jitter that severely impacts ADC dynamic range. For example, reducing the impact of clock jitter by a factor of eight will add three ENOBs for ADCs. At lower clock rates such reductions will provide ENOB benefits until the limit of aperture jitter is reached.